The invention relates to the field of integrated circuit verification, and in particular to methods and apparatus for extracting design and layout information from integrated circuits.
In the semiconductor industry it is often necessary to physically analyze semiconductor integrated circuits (ICs) for the purposes of product reliability assurance, design validation and identification of device structural patterns. ICs are analyzed to extract design and/or layout information therefrom. This process is known as reverse-engineering. Reverse-engineering is also part of the test and development process in the manufacture of ICs on a large scale. In general, a vast amount of time and manual labor is required to reverse-engineer an IC.
An IC is a monocrystalline silicon die upon which a large number of transistors and other electronic components have been fabricated and interconnected to form a useful circuit. During manufacture, each die is part of a larger silicon wafer substrate which facilitates handling and simultaneous processing of a plurality of ICs.
The IC fabrication process includes: doping the silicon substrate to change its conductive properties and building up a sequence of layers onto the silicon substrate using different techniques. Doping layers are created using ion implantation. Diffusion layers are created by depositing dopants on top of a substrate and heating the wafer. With each deposition layer, different materials are deposited and selectively removed by selective etching in accordance with a predetermined pattern. Components manufactured on the silicon wafer span multiple layers. Oxide layers are used for insulation. Deposited metal layers are used to interconnect individual terminals of the components so formed. It is the identification of these components and the interconnections provided by the metal layers that provides base information from which the design and/or layout of an IC can be extracted and verified.
In reverse-engineering a sample IC, the die is deconstructed. The IC sample die is subjected to a progressive layer-removal sequence utilizing an exacting series treatment, such as etchants, each of which is specifically chosen to remove a single layer at a time. Other deconstructing treatments include dry etching, polishing, etc. Using such treatments, interconnecting metal layers, polycrystalline silicon layers, oxide layers, etc. are removed step-by-step. At each step in the deconstruction of a chip, the surface of the partly deconstructed IC is inspected.
Inspection techniques include the use of: optical microscopes, scanning electron microscopes, and other surface inspection equipment. In general, the scanning electron microscope is accurate but is expensive to own and operate. Optical microscopes can be used in brightfield, contrast interference and darkfield modes of illumination. In the brightfield or contrast interference modes, the physical extents of the components on the die are distorted by fringe effects. These fringe effects can be interpreted by an experienced human analyst but require vast amounts of computation for analysis by a computer.
A METHOD OF EXAMINING MICROCIRCUIT PATTERNS is described in the U.S. Pat. No. 4,623,255 which issued Nov. 18, 1986 to Suszko. The method involves photographing an IC die in between deprocessing steps. Film transparencies are printed and used by an engineer analyst to extract design and layout information from the photographed IC. While the teachings of Suszko have merit, design and layout extraction are impeded by the handling and cross-correlation of the bulky transparencies.
Human enabled extraction of design and layout information from image-mosaics is lengthy. Other prior art methods concentrate on eliminating human input from the information extraction process by devising image analysis algorithms.
An AUTOMATED SYSTEM FOR EXTRACTING DESIGN AND LAYOUT INFORMATION FROM AN INTEGRATED CIRCUIT is described by Yu et al. in U.S. Pat. No. 5,086,477 which issued Feb. 4, 1992. A digital camera and a controlled stage are used to capture images in overlapping tile fashion after each deconstruction step. The captured digital images are stored in a computer memory and reassembled into image-mosaics based on the overlap at the borders of each tile image. Yu et al. describe pattern matching performed on an image-mosaic captured after a deconstruction step, and points out the difficulties involved in extracting layout information from the tile images. The automated system to Yu et al. appears to be suitable for extracting design information from complex ICs that are difficult to reverse engineer. To accomplish this, xe2x80x9ccellxe2x80x9d libraries are built. The cell libraries contain images of specific arrangements of components that are known to perform a specific function. The cell libraries are used for automated pattern matching in order to facilitate reverse engineering of Application Specific Integrated Circuits (ASICs), for example. However, Yu et al. fail to describe how multiple image-mosaics, each representing a different step in the deconstruction of an IC, are manipulated in order to extract design and layout information concurrently therefrom. Concurrent analysis of image-mosaics is desirable because individual components fabricated on the silicon wafer may span multiple layers.
Another prior art publication in PROCEEDINGS OF THE 5TH INTERNATIONAL SYMPOSIUM ON IC TECHNOLOGY, SYSTEM AND APPLICATIONS, SINGAPORE by Tan Ooi Kiang et al. entitled xe2x80x9cINTEGRATED CIRCUIT CHIP LAYER ANALYSISxe2x80x9d (presented Sep. 15-17, 1993) describes a system for automatic layout extraction from IC""s achieving a quoted 85% accuracy. The remainder of the extracted layout being left for completion by a human engineer analyst.
While such automated systems are ingenious, it is debatable whether such automated design and layout extraction methods are superior to or more economical than human driven processes.
There therefore is a need to provide improved methods and apparatus enabling an engineer analyst to extract design and layout information from image-mosaics in a time efficient, enhanced manner.
The invention therefore provides a design analysis workstation for analyzing an integrated circuit that has been deconstructed and a digital image-mosaic of the integrated circuit was acquired at each deconstruction step to permit design and layout information to be extracted therefrom. The design analysis workstation comprises means for displaying each image-mosaic in a corresponding mosaic-view; means for displaying an annotation overlay over an image-mosaic in at least one of the mosaic-views; and means for editing annotation objects associated with the annotation overlay.
Each of the image-mosaics is displayed in a respective mosaic-view as a background image to the annotation overlay. The annotation overlay has see-through properties to permit the annotation objects to be created and edited using information derived from at least one underlying image-mosaic. Each one of the annotation objects has associated attributes.
The design analysis workstation includes means for concurrently displaying a plurality of annotation overlays. The display of the plurality of image-mosaics displayed in a respective plurality of mosaic-views is synchronized. The means for synchronizing the display of the plurality of image-mosaics includes means for panning the plurality of image-mosaics by a specified distance that is the same for each image-mosaic. The means for synchronizing the display of the plurality of image-mosaics further includes means for zooming the plurality of image-mosaics by a specified zoom factor that is the same for each of the image-mosaics.
Annotation objects may be edited based on information derived from a plurality of image-mosaics displayed in respective mosaic-views. The editing is facilitated by a plurality of synchronized view-cursors respectively displayed in the plurality of mosaic-views. The synchronized view-cursors move in lock-step with a master-cursor displayed in a one of the mosaic-views. The master-cursor is controlled by a pointing device operatively associated with the design analysis workstation.
The design analysis workstation further comprises image-mosaic comparison means for comparing selected portions of image-mosaics displayed in a plurality of mosaic-views. The image-mosaic comparison means includes an image-mosaic comparison view displaying respective portions of the image-mosaics. Each mosaic-view includes an annotation overlay selector.
Annotation objects have a respective predetermined group of attributes. Each annotation object comprises at least one layer attribute. A wire annotation object comprises an associated layer attribute and signal carrying characteristics. The layer attributed associated with the wire annotation object may specify a layer different from the image-mosaic associated with the annotation overlay with which the wire annotation object is associated. A contact annotation object comprises two associated layer attributes, the contact annotation object specifying inter-layer connectivity using the two associated layer attributes.
An annotation object may also have annotation properties. Each annotation property is preferably editable. The annotation properties are preferably also extensible. The annotation properties may be, for example, key-value pairs.
The design analysis workstation provides means for performing operations on selected annotation objects and means for performing measurements of selected features of an image-mosaic. The means for performing measurements includes means for performing linear measurements and means for performing area measurements.
The design analysis workstation permits selected annotation objects to be aggregated into annotation object groups. The design analysis workstation provides means for associating properties with the annotation object group(s). The annotation properties associated with an annotation object group may override annotation properties associated with individual annotation objects aggregated into the annotation object group. An annotation object group may comprise a collection of at least two annotation object groups. An annotation object group further includes a cell specification. The cell specification specifies at least one port. A port of a cell has signal directionality. The signal directionality comprises any one of input signaling, output signaling and bi-directional signaling.
In accordance with the invention, there is further provided a system for extracting design and layout information from a plurality of image-mosaics representative of a deconstructed integrated circuit. The system comprises means for enabling parallel design analysis of the image-mosaics by a plurality of engineer analysts concurrently reverse engineering an IC. The plurality of image-mosaics are annotated concurrently using a plurality of design analysis workstations. Each one of the annotation objects created using a design analysis workstation participating in parallel design analysis includes an ownership attribute that specifies an engineer analyst associated with the design analysis workstation at a time when the annotation object was created. Each annotation object includes an identification string, and the system further comprises means for generating unique identification strings. Annotation objects having different ownership attributes can be merged for display on one design analysis workstation.
The invention further provides a method of analyzing the layout of a deconstructed circuit using a design analysis workstation, comprising a step of performing at least one edit operation on at least one annotation object associated with an annotation overlay superimposed over an image-mosaic captured after one step in deconstructing the integrated circuit, the image-mosaics being displayed in at least one of a plurality of concurrently displayed mosaic-views. Performing the edit operation on the annotation object comprises a step of creating the annotation object before the edit operation is performed. Creating the at least one annotation object may be accomplished by drawing at least one schematic. The design analysis workstation associates the created annotation object with an annotation overlay in which the operation to create the annotation object was started.
A wire annotation object may also be created. Wire annotation objects are associated with a layer. The wire annotation object represents a signal carrier. A connection annotation object may likewise be created. The connection annotation object is associated with first and second layers of the integrated circuit. The connection annotation object represents signal connectivity between other annotation objects.
Performing an edit operation on an annotation object may further comprise a step of modifying the annotation object. Modifying the annotation object may further comprise a step of associating the annotation object with an annotation overlay in which an edit operation that moved the annotation object ended. Modifying the annotation object may also comprise a step of associating the annotation object with an annotation overlay in which an edit operation that copied the annotation object ended. Modifying the annotation object may yet further comprise a step of hiding the annotation object from being displayed, in order to prevent accidental editing thereof. Modifying the annotation object may also comprise a step of locking the annotation object, to prevent further modification thereof.
The method further comprises a step of saving at least one annotation object independently of the annotation overlays associated with the respective image-mosaics. The method also comprises a step of loading the at least one saved annotation object independently of the annotation overlays associated with the respective image-mosaics. The method likewise comprises a step of selecting at least one annotation object for inclusion in a selection group. Selecting the at least one annotation object further comprises steps of: pointing at the at least one annotation object using a pointing device associated with the design analysis workstation; and manipulating one of the pointing device and at least one key of the design analysis workstation to select the at least one annotation object for inclusion in the selection group. Selecting the at least one annotation object for inclusion in the selection group may be performed using an annotation object search. Subsequent to selecting the at least one annotation object for inclusion in the selection group, the mosaic-views may be automatically panned or zoomed to display the selected annotation object(s).
Performing the edit operation on a selection group further comprises grouping selected annotation objects in the selection group to form an annotation object group. The method also comprises a step of performing at least one edit operation on the annotation object group. The method also comprises a step of undoing at least one edit operation performed on the at least one annotation object. Performing the edit operation further comprises a step of redoing at least one edit operation performed on the at least one annotation object.
The method in accordance with the invention also comprises steps of creating an annotation property, and associating the annotation property with the at least one annotation object. The method further comprises a step of editing the annotation property associated with the annotation object. The annotation property is preferably displayed in an annotation object information pop-up window. The annotation object information pop-up window may be configured to persist, pending an action to close the window.
The method further comprises a step of defining at least one cell for performing design and layout extraction. The cell comprises at least one annotation object. A cell may also include at least one annotation object group.
The present invention further provides a method of analyzing a design of a deconstructed integrated circuit using a design analysis workstation. The method comprises a step of propagating signal information from an annotation object having a signal property to at least one other connected annotation object. Signal information is propagated between a cell and a wire annotation object. The method also comprises a step of generating a net-list from interconnected cells.
Propagating signal information in accordance with the invention comprises steps of selecting all contact annotation objects connected to a wire annotation object, the wire annotation object and the contact annotation objects having at least one specified layer in common; and, propagating signal information from the wire annotation object to all annotation objects connected to the contact annotation objects. The method further comprises a step of detecting a logical short if two different signals are propagated to a given annotation object. On detecting the logical short, the method further comprises a step of displaying information about the logical short on the design analysis workstation.